Aldec and Synplicity Expand OEM Agreement

Contact Person: Megan Moran
Aldec, Inc.
702.990.4400, ext. 201
meganm@aldec.com


Henderson Nevada, October 29th, 2001-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) in conjunction with Synplicity (NASDAQ: SYNP), a leading supplier of software for the design and verification of semiconductors, announced today a further expansion of their OEM product bundling announced in August. The companies will now offer Synplicity's HDL Analyst(r) tool as an add-on feature to the Active-HDL with Synplify(r) bundle.

Aldec initially offered Aldec's FPGA design entry and mixed VHDL, Verilog and EDIF simulation product together with Synplicity's industry-leading Synplify synthesis tool. The success of the integrated package stimulated both companies to broaden the product offering and give designers additional advancements in the EDA industry.

"Aldec and Synplicity thought it would be in customers' best interests to broaden the scope of the initial OEM agreement and offer the HDL Analyst software as an option. This will particularly benefit users with high-density designs," stated Megan Moran, Product Marketing Manager for Active-HDL.

Joe Gianelli, director of business development and strategic alliances for Synplicity, added, "Our HDL Analyst tool offers a unique solution for design debugging and analysis, and we are pleased to expand our relationship with Aldec to offer the tool with the Active-HDL with Synplify bundle. Using the HDL Analyst tool within this flow, we believe designers will be able to achieve higher performance and improve their own productivity."

The HDL Analyst tool generates a hierarchical RTL block diagram of a design directly from HDL code. This high level of graphical abstraction shows designers where improvements can be made in the original HDL source code to enhance the efficiency and performance of the design. Synplicity's HDL Analyst tool provides effective navigation for the entire design and allows users to view a graphical representation of the design and modify it accordingly. The primary benefit of the HDL Analyst tool is that it provides users with a concurrent view of three different design representations; the design can be expressed as HDL code, a technology-independent RTL block diagram and a technology-specific view.

The HDL Analyst tool's effective debugging features alert the designer to critical portions of the design and then automatically highlights these sections. From here the code is easily modified and the design cycle can proceed with fewer obstacles. Once errors and inefficiencies in the design have been corrected, the design will operate with improved accuracy and performance. By offering the HDL Analyst tool as an option for the Active-HDL with Synplify bundle, the concept of uniting simulation and synthesis can now support even the most complex FPGA designs.

Availability
Aldec is currently offering the Active-HDL with Synplify bundle, and the HDL Analyst tool is now available as an add-on option. The product is available as either a floating or node-lock license and includes Aldec's HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation as well as Synplicity's Synplify synthesis tool. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.

About Synplicity
Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in next-generation networking and communications hardware and other electronic devices. The company leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. Synplicity's fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of June 30, 2001, Synplicity employed over 250 people in its 16 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif.

Active-HDL is a trademark of Aldec, Inc. Synplicity, Synplify and HDL Analyst are registered trademarks of Synplicity, Inc. All other trademarks or registered trademarks are property of their respective owners